diff -Nru trafficserver-5.0.1/debian/changelog trafficserver-5.0.1/debian/changelog --- trafficserver-5.0.1/debian/changelog 2014-07-23 16:13:29.000000000 +0000 +++ trafficserver-5.0.1/debian/changelog 2015-03-29 02:32:50.000000000 +0000 @@ -1,3 +1,9 @@ +trafficserver (5.0.1-1+rpi1) jessie-staging; urgency=medium + + * Add armv6 asm for memory barriers. + + -- Peter Michael Green Sun, 29 Mar 2015 02:31:47 +0000 + trafficserver (5.0.1-1) unstable; urgency=medium * New upstream release including a fix for CVE-2014-3525 that allowed diff -Nru trafficserver-5.0.1/debian/patches/series trafficserver-5.0.1/debian/patches/series --- trafficserver-5.0.1/debian/patches/series 2014-07-05 12:41:59.000000000 +0000 +++ trafficserver-5.0.1/debian/patches/series 2015-03-29 02:38:35.000000000 +0000 @@ -0,0 +1 @@ +support-armv6.patch diff -Nru trafficserver-5.0.1/debian/patches/support-armv6.patch trafficserver-5.0.1/debian/patches/support-armv6.patch --- trafficserver-5.0.1/debian/patches/support-armv6.patch 1970-01-01 00:00:00.000000000 +0000 +++ trafficserver-5.0.1/debian/patches/support-armv6.patch 2015-03-29 02:39:25.000000000 +0000 @@ -0,0 +1,31 @@ +Description: Add armv6 asm for memory barriers. + armv6 doesn't have dmb but it does have a coprocessor instruction that + provides the same function. +Author: Peter Michael Green + +--- +The information above should follow the Patch Tagging Guidelines, please +checkout http://dep.debian.net/deps/dep3/ to learn about the format. Here +are templates for supplementary fields that you might want to add: + +Origin: , +Bug: +Bug-Debian: https://bugs.debian.org/ +Bug-Ubuntu: https://launchpad.net/bugs/ +Forwarded: +Reviewed-By: +Last-Update: + +--- trafficserver-5.0.1.orig/plugins/header_rewrite/lulu.h ++++ trafficserver-5.0.1/plugins/header_rewrite/lulu.h +@@ -45,6 +45,10 @@ char* getIP(sockaddr const* s_sockaddr, + #define mb() __asm__ __volatile__ ( "sync" : : : "memory") + #define rmb() __asm__ __volatile__ ( "sync" : : : "memory") + #define wmb() __asm__ __volatile__ ( "" : : : "memory") ++#elif defined(__ARM_ARCH_6__) ++#define mb() __asm__ __volatile__ ( "mcr p15, #0, r0, c7, c10, #5" : : : "memory") ++#define rmb() __asm__ __volatile__ ( "mcr p15, #0, r0, c7, c10, #5" : : : "memory") ++#define wmb() __asm__ __volatile__ ( "" : : : "memory") + #elif defined(__arm__) + #define mb() __asm__ __volatile__ ( "dmb" : : : "memory") + #define rmb() __asm__ __volatile__ ( "dmb" : : : "memory")