diff -Nru chromium-83.0.4103.116/debian/changelog chromium-83.0.4103.116/debian/changelog
--- chromium-83.0.4103.116/debian/changelog	2020-09-15 13:10:35.000000000 +0000
+++ chromium-83.0.4103.116/debian/changelog	2020-12-16 04:45:43.000000000 +0000
@@ -1,3 +1,9 @@
+chromium (83.0.4103.116-3.1+rpi1) bullseye-staging; urgency=medium
+
+  * Add upstream patch to fix build with newer clang (closes: 977103)
+
+ -- Peter Michael Green <plugwash@raspbian.org>  Wed, 16 Dec 2020 04:45:43 +0000
+
 chromium (83.0.4103.116-3.1) unstable; urgency=medium
 
   * Non-maintainer upload.
diff -Nru chromium-83.0.4103.116/debian/patches/avoid-r7-as-an-input-register-to-asm.patch chromium-83.0.4103.116/debian/patches/avoid-r7-as-an-input-register-to-asm.patch
--- chromium-83.0.4103.116/debian/patches/avoid-r7-as-an-input-register-to-asm.patch	1970-01-01 00:00:00.000000000 +0000
+++ chromium-83.0.4103.116/debian/patches/avoid-r7-as-an-input-register-to-asm.patch	2020-12-16 04:45:13.000000000 +0000
@@ -0,0 +1,49 @@
+Paths adjusted to apply to the Debian chromium package
+by Peter Michael Green.
+
+commit 00604cd2806b5d26bef592dd19989a234bd07a4b
+Author: Amy Huang <akhuang@google.com>
+Date:   Thu Apr 23 11:25:53 2020 -0700
+
+    Remove use of register r7 because llvm now issues an
+    error when "r7" is used (starting in commit d85b3877)
+    
+    Bug: chromium:1073270
+    Change-Id: I7ec8112f170b98d2edaf92bc9341e738f8de07a3
+    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2163435
+    Reviewed-by: Nico Weber <thakis@chromium.org>
+    Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
+    Commit-Queue: Nico Weber <thakis@chromium.org>
+    Cr-Commit-Position: refs/heads/master@{#67371}
+
+diff --git a/v8/src/codegen/arm/cpu-arm.cc b/v8/src/codegen/arm/cpu-arm.cc
+index 9113de705d..47fe4bdb74 100644
+--- a/v8/src/codegen/arm/cpu-arm.cc
++++ b/v8/src/codegen/arm/cpu-arm.cc
+@@ -37,18 +37,6 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
+   register uint32_t end asm("r1") = beg + size;
+   register uint32_t flg asm("r2") = 0;
+ 
+-#ifdef __clang__
+-  // This variant of the asm avoids a constant pool entry, which can be
+-  // problematic when LTO'ing. It is also slightly shorter.
+-  register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
+-
+-  asm volatile("svc 0\n"
+-               :
+-               : "r"(beg), "r"(end), "r"(flg), "r"(scno)
+-               : "memory");
+-#else
+-  // Use a different variant of the asm with GCC because some versions doesn't
+-  // support r7 as an asm input.
+   asm volatile(
+       // This assembly works for both ARM and Thumb targets.
+ 
+@@ -66,7 +54,6 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
+       : "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
+       : "memory");
+ #endif
+-#endif
+ #endif  // !USE_SIMULATOR
+ }
+ 
diff -Nru chromium-83.0.4103.116/debian/patches/series chromium-83.0.4103.116/debian/patches/series
--- chromium-83.0.4103.116/debian/patches/series	2020-09-15 12:50:25.000000000 +0000
+++ chromium-83.0.4103.116/debian/patches/series	2020-12-16 04:45:26.000000000 +0000
@@ -88,3 +88,4 @@
 use-explicit-python2-sed.patch
 use-explicit-python2-gn.patch
 allow-time64-syscalls.patch
+avoid-r7-as-an-input-register-to-asm.patch